edi8l32128v 128kx32 sram 3.3 volt 1 edi8l32128v rev. 1 4/97 eco #8366 features 128kx32 cmos high speed static ram 128kx32 bit cmos static analog sharc tm external memory solution ? adsp-21060l ? adsp-21062l random access memory array ? fast access times: 12,15 and 20ns ? user configurable organization with minimal additional logic ? master output enable and write control ? ttl compatible inputs and outputs ? fully static, no clocks surface mount package ? 68 lead plcc, no. 99 (jedec mo-47ae) ? small footprint, 0.990 sq. in. ? multiple ground pins for maximum noise immunity single 3.3v (5%) supply operation pin configurations and block diagram pin names the edi8l32128v is a high speed, 3.3 volt, four megabit density static ram. the device is available with access times of 12, 15 and 20ns, allowing the device to support 60mhz dsps with no wait states. the high speed, 3.3v supply voltage and byte configurability make the device ideal for interfacing with analog devices adsp-21062l or adsp-21060l sharc dsps. the device can be configured as a 128kx32 and used to create a single chip external data memory solution for the sharc (figure 1). providing a 51% space savings when compared to four 128kx8, 400mil wide plastic sojs. the edi8l32128v has a 10pf load on the data lines vs. 24pf for four plastic sojs. memory upgrades in the same footprint can be accomplished with the edi8l32256v (256kx32) or the edi8l32512v (512kx32). this is covered in detail in the application report "the edi's x32 mcm-l sram family: integrated memory solution for the analog sharc dsp" alternatively the device's chip enables can configure it as a 256kx16. a 256kx48 program memory array for the sharc is created using three devices (figure 2). if this memory is too deep, two 128kx24's (edi8l24128v) can be used to create a 128kx48 memory array. note: solder reflow temperature should not exceed 260c for 10 seconds a?-a16 address inputs e?-e3 chip enables (one per byte) w master write enable g master output enable dq?-dq31 common data input/output vcc power (+3.3v10%) vss ground nc no connection 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dq17 dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq28 dq29 dq30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 dq14 dq13 dq12 vss dq11 dq10 dq9 dq8 vcc dq7 dq6 dq5 dq4 vss dq3 dq2 dq1 dq31 27 a6 28 a5 29 a4 30 a3 31 a2 32 a1 33 a? 34 vcc 35 a13 36 a12 37 a11 38 a10 39 a9 40 a8 41 a7 42 dq? 43 9 dq16 8nc 7nc 6e3\ 5e2\ 4e1\ 3e?\ 2nc 1vcc 68 nc 67 nc 66 g\ 65 w\ 64 a16 63 a15 62 a14 61 dq15 a -a16 g w e e1 e2 e3 17 128kx32 memory array dq -dq7 dq8-dq15 dq16-dq23 dq24-dq31 note: pin 2 & 67 on the 64kx32 (edi8l3265c) and the 256kx32 (edi8l32256c) are word select pins. electronic designs incorporated ? one research drive ? westborough, ma 01581 usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com
2 edi8l32128v rev. 1 4/97 eco #8366 edi8l32128v 128kx32 sram 3.3 volt absolute maximum ratings* recommended dc operating conditions parameter sym min typ max units supply voltage vcc 3.135v 3.3 3.465v v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc+0.3 v input low voltage vil -0.3 -- 0.8 v voltage on any pin relative to vss -0.5v to 4.6v operating temperature ta (ambient) commercial 0c to + 70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 3 watts output current. 20 ma junction temperature, tj 175c *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics parameter sym conditions min max units 12 15 20 ns operating power supply current icc1 w= vil, ii/o = 0ma, 680 660 620 ma min cycle standby (ttl) supply current icc2 e ? vih, vin- vil or 120 120 120 ma vin ? vih, f=?mhz full standby cmos icc3 e ? vcc-0.2v 40 40 40 ma supply current vin ? vcc-0.2v or vin - 0.2v input leakage current ili vin = 0v to vcc 10 a output leakage current ilo v i/o = 0v to vcc 10 a output high volltage voh ioh = -4.0ma 2.4 v output low voltage vol iol = 8.0ma 0.4 v capacitance (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ca 40 pf data lines cd/q 10 pf write & output enable lines w, g 40 pf chip enable lines e?-e3 8 pf these parameters are sampled, not 100% tested. ac test conditions (note: for tehqz,tghqz and twlqz, cl = 5pf) (see figure 2) input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 g e w mode output power x h x standby high z icc2,icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 typical: ta = 25c, vcc = 3.3v truth table figure 1 figure 2 353 w vcc 5 pf 319 w dout q z0 = 50 w r l = 5 0 w v l = 1.5v 65 pf
edi8l32128v 128kx32 sram 3.3 volt 3 edi8l32128v rev. 1 4/97 eco #8366 ac characteristics read cycle symbol 12ns 15ns 20ns parameter jedec alt. min max min max min max units read cycle time tavav trc 12 15 20 ns address access time tavqv taa 12 15 20 ns chip enable access time telqv tacs 8 10 20 ns chip enable to output in low z (1) telqx tclz 2 3 3 ns chip disable to output in high z (1) tehqz tchz 7 8 10 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 5 6 8 ns output enable to output in low z (1) tglqx tolz 2 2 2 ns output disable to output in high z(1) tghqz tohz 4 5 8 ns read cycle 2 - w high read cycle 1 - w high, g, e low note 1: parameter guaranteed, but not tested. tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv
4 edi8l32128v rev. 1 4/97 eco #8366 edi8l32128v 128kx32 sram 3.3 volt note 1: parameter guaranteed, but not tested. write cycle 1 - w controlled symbol 12ns 15ns 20ns parameter jedec alt. min max min max min max units write cycle time tavav twc 12 15 20 ns chip enable to end of write telwh tcw 8 9 15 ns teleh tcw 8 9 15 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 9 10 15 ns taveh taw 9 10 15 ns write pulse width twlwh twp 9 10 15 ns twleh twp 9 10 15 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 050607 ns data to write time tdvwh tdw 5 6 8 ns tdveh tdw 5 6 8 ns output active from end of write (1) twhqx twlz 2 2 2 ns a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax ac characteristics write cycle
edi8l32128v 128kx32 sram 3.3 volt 5 edi8l32128v rev. 1 4/97 eco #8366 a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh package no. 99 68 lead plcc jedec mo-47ae theta j a =40c/w theta j c =15c/w weight =4.2g package description ordering information write cycle 2 - e controlled 0.956 max 0.180 max 0.115 max 0.040 max 0.050 bsc 0.020 0.015 0.995 max 0.930 0.890 0.956 max 0.995 max part number speed package (ns) no. EDI8L32128V12AC 12 99 edi8l32128v15ac 15 99 edi8l32128v20ac 20 99 part number speed package (ns) no. edi8l32128v12ai 12 99 edi8l32128v15ai 15 99 edi8l32128v20ai 20 99 commercial (0c to 70c) industrial (-40c to +85c) electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301
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